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ORCID38th VLSI Design 2025: Bangalore, India
- 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, VLSID 2025, Bangalore, India, January 4-8, 2025. IEEE 2025, ISBN 979-8-3315-2244-5
- Aakashjit Bhattacharya
, Arnab Sarkar, Ansuman Banerjee:
MERGERS: Multi-Access Edge Resource Governance for Real-Time SaaS Systems. 1-6 - Sourav Das, Aritra Hazra, Pallab Dasgupta, Himanshu Jain, Sudipta Kundu:
PrOFraC: Property Ordering and Frame Clause Reuse for Multi-Property Verification. 7-12 - Tamal Chowdhury, Pradip Mandal:
Bidirectional Spiking Neuron Based Dual-Mode Signal Acquisition Front-End System. 13-18 - Prakhar Diwan, Nirmal Kumar Boran, Virendra Singh:
Lichen: Leveraging Coupled Heterogeneity. 19-24 - Sourav Saha, Anmol Khatri, Lalit Arora, Raj Yadav, Rakshit Bazaz:
Physical Synthesis Optimization Prediction Using Machine Learning. 25-30 - B. Naresh Kumar Reddy, Srinivasulu Jogi, Yellapragada Charan Krishna:
Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping. 31-36 - Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET. 37-42 - Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler:
FARAD: Automated Formal Verification of Approximate Restoring Array Dividers. 43-48 - Alip Majumdar, Rahul Shrestha:
CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber. 49-54 - Soumick Majumdar, Anshul Madurwar, Anmol Shetty, Kurian Polachan:
hbcLock: Encrypted RF Communication Utilizing Body-Coupled Keys for the Internet of Bodies. 55-60 - Jitesh Choudhary, Imran Hussain Barbhuiya, Dharrun Singh. M, Soumya J.:
FRoZN: Fault-Tolerant Routing Technique Using Reinforcement Learning for ZMesh NoC. 61-66 - Mohammed Musayyeb Sherwani, Mohammad Abdul Azeem, Mohammed Usman, Siddique Ahmad, Mujeev Khan, R. Shamim, Mohd Wajid:
Optimal Respiratory Rate Estimation with mmWave Sensing Using PYNQ System-on-Chip Platform. 67-72 - Divyansh Singhal, Yash Gupta, Daksh Sharma, Chinmay Sultania, Madhav Rao:
HapticGuide: Interactive Wearable Braille Guide for Enhancing Visual Education. 73-78 - Sourav Saha, Sagar Rana, Keshav Patil, Nagamaheswar Harivelam Srinivas Gari:
Interconnect Optimization for Timing and Power [IOTAP]. 79-84 - Alexander Kharitonov, Sandip Kundu:
A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination. 85-90 - N. S. Aswathy, Harsh Verma, Hemangee K. Kapoor:
Optimizing Bandwidth Utilization Through Word Based Compression in Main Memories. 91-96 - Chaitanya Modiboyina, Syam Babu Gundumilli, Soumya Kanti Ghosh, Indrajit Chakrabarti:
Accelerating U-Net: A Patchwise Memory Optimization Approach for Image Segmentation. 97-102 - Soumojit Bakshi, V. K. Surya, Nijwm Wary:
Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICs. 103-108 - Hemangee K. Kapoor, Kartikay Bhardwaj:
ABMF: Adaptive Bonsai Merkle Forests for Efficient Integrity Verification in Secure Persistent Memories. 109-114 - Bollam Shiva Prasad, Mahima Arrawatia:
A 0.27-THz Frequency Multiplier Chain Using Harmonic Mixing with Multiplication of × 18 in 65-nm CMOS. 115-120 - Daksh Sharma, D. R. Vasanthi, Sanampudi Gopala Krishna Reddy, Madhav Rao:
NSGA-RM: NSGA-II Evolved Performance Optimized Non-Homogeneous Recursive Polynomial Multiplier Architectures. 121-126 - L. Hemanth Krishna, Sreehari Veeramachaneni, Srinivasu Bodapati, Bhaskara Rao Jammu, Sk. Noor Mahammad:
Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor. 127-132 - Hari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo:
TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface. 133-138 - Jugal Gandhi, Nikhil Handa, Abhay Nayak, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey:
SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation. 139-144 - Dhayan Dhananjaya Senanayake, Priyanshu Tyagi, Sparsh Mittal, Rekha Singhal:
An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery Computing. 145-150 - Abhinav S, Busam Karthikeya, Ishan Acharyya, Anushka Tripathi, Abhishek Srivastava:
Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency Synthesizers. 151-156 - Priyatam Roy, Surinder Sood:
Boosting System-on-Chip Performance Through AI-Assisted Optimization Using Compositional Neural Networks. 157-162 - Soumik Guha Roy, Adriz Chanda, Prateek Ganguli, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran:
BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware Circuits. 163-168 - Velamala Pavan Kumar, Aravindhan Alagarsamy:
A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGA. 169-174 - Chaya Hegde, Arun Mohan, Saroj Mondal, Roy P. Paily:
A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting Systems. 175-179 - Dimple Vijay Kochar, Maitreyi Ashok, Anantha P. Chandrakasan:
A 0.75mm2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices. 180-185 - Subbareddy Chavva, Immanuel Raja:
N-Well Patterning of P-Type CMOS Substrate for Improving Quality Factor of on-Chip Inductors at Millimeter Wave Frequencies. 186-190 - Chiragkumar B. Patel, Ajay Kumar Singh, Himanshu N. Patel, B. Saravana Kumar:
Serialized Control Interface ASIC for Distributed Controllers of Space-Borne RADAR. 191-196 - Lutz Schammer, Gianluca Martino, Görschwin Fey:
DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs. 197-202 - Deepesh Gujjar, Sanatkumar Upadhye, Sandipan Sinha, Taha Khursheed, Jigar Patel, Jaswinder Sidhu, Manish Trivedi, Sagar Abachi:
An Innovative Solution to Improve Ultra Low Voltage Writability and Leakage in GPU SRAMs. 203-207 - Y. Anu rajarajeswari, Nitin Chandrachoodan, Anji Babu Vadapalli, J. Klutto Milleth:
Hardware Implementation of Blind Decoding of Downlink Control Information for 5G. 208-213 - Anubhav Srivastava, Sadique Mohammad Iqbal, Divya Tripathi, Saurabh Goyal:
Startup Circuit for Relaxation Oscillators with Low Functional Current and Minimal Area. 214-218 - MC Balasubramaniam, Basava Naga Girish Koneru, Nitin Chandrachoodan:
Effective Memory Management and Sparse Aware Cache for Row-Wise Sparse CNNs. 219-224 - Himanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao:
FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs. 225-230 - Kushagra Singh, Kafil Abbas Momin, Anshul V. Patil, Madhav Rao:
Advancing Rehabilitation Through Low Weight Hand Assistive System: Design and Impact Analysis. 231-236 - Amit Singh, Amit Kumar Jangid, B. Srinivasu:
Advancing Neural Network Performance with Probabilistic Computing for ReLU Function. 237-242 - Hemangee K. Kapoor, Imlijungla Longchar, Binayak Behera:
E-DOSA: Efficient Dataflow for Optimising SNN Acceleration. 243-248 - Vinay Rayapati, Mahati Basavaraju, Madhav Rao:
Layer-Specific Hardware Pooling Designs for CNN Accelerators. 249-254 - Mrinmoy Mahapatra, Prathamesh Ganesh Kekarjawlekar, Akshay K.:
TCAD Based Study of String Current Variability in 3D NAND Flash Memory. 255-260 - C. Bhagyalakshmi, Madhav Lekkala, Maneesh Pandey:
Early Bug Detector - A Verification Methodology for DFD-SoC RTL Parameters. 261-265 - Swati Upadhyay, Hemangee K. Kapoor:
PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories. 266-271 - Sandeep Kumar, Abhisek Panda, Advait Nerlikar, Smruti R. Sarangi:
A Tug-of-War Between Static and Dynamic Memory in Intel SGX. 272-277 - Abhishek Yadav, Vyom Kumar Gupta, Kethireddy Harshith Reddy, Masahiro Fujita, Binod Kumar:
Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications. 278-283 - Rouf Rahman Sheikh, Ram Krishna Ghosh:
Tunnel Magnetoresistance in Strained L10-FeAu Perpendicular Magnetic Tunnel Junction. 284-289 - Kowshic A. Akash, Tobias Wulf, Torsten Valentin, Alexander Geist, Ulf Kulau, Sohan Lal:
AI-Driven Anomaly Detection in Oscilloscope Images for Post-Silicon Validation. 290-295 - Koustubh Phalak, Swaroop Ghosh:
QuaLITi: Quantum Machine Learning Hardware Selection for Inferencing with Top-Tier Performance. 296-301 - Ravuru Vasudeva Reddy, Siva Kumar Rapina, Siddhartha Hazra, K. Sarangam:
8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process. 302-307 - Cheryl Mary Joyce, Parag Upadhyay, Sashank Nishad, Abhimanyu Kakkar:
PPA-Aware Power Grid Optimization Techniques for Congested High Frequency Datapath Designs. 308-313 - J. Chithambara Moorthii, Anmol Singla, Manan Suri:
DNA-CIM: DNA Sequence Analysis Using RRAM-Based Compute In-Memory Accelerator. 314-319 - Ritan Das, Basudev Majumder:
K Band High Power Broadband AlGaN/GaN HEMT Balanced Power Amplifier for Satellite Transponder. 320-325 - D. V. Bhargav, G. Pradyumna, Madhav Rao:
Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design. 326-331 - Shivani Jayakumar, Prasanth Viswanathan Pillai, Sumit Kumar Mandal:
Accelerated Design Verification Coverage Closure Using Machine Learning. 332-337 - Arun Mohan, Saroj Mondal, Yash N. Rayudu, Roy P. Paily:
Low Form-Factor Switchless Dual-Band Matching Network for RF Power Harvesting Systems. 338-343 - Jaspreet Singh, Aakash Kumar Jain, Mamidala Jagadesh Kumar:
Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs. 344-350 - Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay:
Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network. 351-356 - Praveen Verma, Anuj Dhillon, Ashfaque Ahmed, Yagnesh Vaderiya, Chandan Singh, Veenita Kumari, Harshit Sharma:
CMOSP18 FD-SOI Technology Based MCU Achieving High Performance of 1.2GHz Using High Speed, Optimized Leakage & High Density Tightly Coupled Memory (TCM). 357-361 - Siva Chinmai Varma Bhupathiraju, Sridhara Sai Krishna, Yashwanth Komuravelly, Ramakant Yadav:
Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI Applications. 362-367 - Shreehari Jagadeesha, Edward Andert, Aviral Shrivastava:
TIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Intersection Cameras. 368-373 - Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli:
Symmetry-Based Synthesis for Interpretable Boolean Evaluation. 374-379 - Harivinay Kancharla, Sounil Biswas:
A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute Clusters. 380-385 - R. Arundeepakvel, Ankesh Jain:
Analysis and Design Considerations for MASH of Noise Shaped SAR ADCs. 386-391 - Varun Darshana Parekh, Yi Xiao, Yixin Xu, Zijian Zhao, Zhouhang Jiang, Rudra Biswas, Sumitha George, Kai Ni, Vijaykrishnan Narayanan:
A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture. 392-397 - Sushmi R, Priya K, Binsu J. Kailath:
Atrial Flutter Detection System by AdEx Encoded Lead-II ECG. 398-403 - Ritwika Majumdar, Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal:
Codesign for Broadcast Addressing Biochip Towards Tamper-Resistance and Enhanced Reliability. 404-409 - Amurt Prakash, Abhijeet Singh, Pooja Madhusoodhanan, Padma Arvind, Viswanathan Pillai Prasanth, Sanjay Das, Kanad Basu:
Advancing Functional Safety: Improving Failure Mode Analysis and Fault Injection Using Automation and GNN Algorithms. 410-415 - Sumanta Chakraborty, Debajyoti Mandal, SK Hafizul Islam:
Quantum Analysis of LESCA. 416-420 - Banit Negi, Muthusamy Hariharan, Vivek Kumar:
2D Thermal Contour Modeling of 14 nm SOI FinFET Using Machine Learning for Efficient Thermal Profile Prediction. 421-426 - Uday Kiran Pedada, Tarun Sharma, Deepank Grover, Sujay Deb:
An Efficient RISC-V Vector Coprocessor for Heart Rate Variability Detection on Edge. 427-432 - Soham Adhikary, Ayan Palchaudhuri:
Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion. 433-438 - Vaikunth Muthuraman, Khushwant Sehra, Vandana Kumari, Manoj Saxena:
An Ensemble MLP-RF Model for the Prediction of DG-MOSFETs: Addressing Fabrication Process Variations. 439-444 - Luigi Capogrosso, Enrico Fraccaroli, Marco Cristani, Franco Fummi, Samarjit Chakraborty:
LO-SC: Local-Only Split Computing for Accurate Deep Learning on Edge Devices. 445-450 - Gaurav Shah, Abhinav Goud, Zaqi Momin, Joycee Mekie:
OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization. 451-456 - Ruby Mishra, Manish Okade, Kamalakanta Mahapatra:
Novel Hardware Architectures for PRESENT Block Cipher and its FPGA Realizations. 457-462 - Monika Pokharia, Het Trivedi, Siddharth Doshi, Ravi S. Hegde, Joycee Mekie:
HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications. 463-468 - Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa:
TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level. 469-474 - Vardhan Suroshi, Karthik B. K, Vikram Kannur, Vinay Reddy, Madhura Purnaprajna:
Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs. 475-480 - Lalit Sharma, Neeraj Goel:
RISC-V Based Secure Processor Architecture for Return Address Protection. 481-486 - Aakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins:
A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction. 487-492 - Santosh Kumar, Ayan Palchaudhuri:
Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA. 493-498 - Indranil Maity, Soubarno Chatterjee, Souvik Bhanja:
A First-Principles-Based Comparative Study Between Pristine and Au-Modified Graphene Nanosheet Towards Acetaldehyde Sensing Performance. 499-504 - Rajat Kohli, Umang Deep, Vaishnavi Holla, Jwalant Kumar Mishra:
Robust Verification Methodology for Scan Chain in Memories. 505-509 - Nishant Kumar, Hari Shanker Gupta, Nihar Ranjan Mohapatra:
Reliable High-Performance Programmable Voltage Regulator with 0.55A Sink Current for Cryo-Cooler Electronics in 0.18μm HV-CMOS Technology. 510-515 - Maeesha Binte Hashem, Benjamin Parpillon, Divake Kumar, Dinithi Jayasuriya, Amit Ranjan Trivedi:
TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products. 516-521 - K. Chitra, Arjun Dey, Aryabartta Sahu:
Efficient Mitigation of DRAM Row Buffer Conflict Using Request Clustering in Manycore Systems. 522-527 - Shivam Agarwal, Sivasai Guddanti, Qadeer A. Khan:
A Fully Autonomous 1.2A Auxiliary Buck DC-DC Converter for Fast Transient Load-on-Demand. 528-533 - Shri Janani Senthil, B. Srinivasu:
MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors. 534-539 - Satanu Maity, Manojit Ghose, Avinash Kumar, Anol Chakraborty, Ankit Chakraborty:
Unguided Machine Learning-Based Computation Offloading for Near-Memory Processing. 540-545 - Sutirtha Bhattacharyya, Fedrick Nongpoh, Karthik Maddala, E. Bhawani Eswar Reddy, Chandan Karfa:
LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models. 546-551 - Pikul Sarkar, Nitin Gupta, Pallat Aravind, Bhavin Odedara, Dror Shahar:
Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSD. 552-557 - Subrata Das, Avimita Chatterjee, Swaroop Ghosh:
Investigating Impact of Bit-flip Errors in Control Electronics on Quantum Computation. 558-563 - Nirmala N, D. Gracia Nirmala Rani:
Enhancing Digital Microfluidic Biochip Operations with Scheduling Interval Method. 564-568 - Anshul Awasthi, Soumi Saha, Parikshit Sahatiya, Surya Shankar Dan:
An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural Network. 569-574 - Aya G. Amer, Maitreyi Ashok, Xin Zhang, John Cohn, Anantha P. Chandrakasan:
A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator. 575-580
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