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ORCIDISSCC 2015: San Francisco, CA, USA
- 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. IEEE 2015, ISBN 978-1-4799-6223-5
- Anantha P. Chandrakasan, Hoi-Jun Yoo:
Session 1 overview: Plenary session. 6-7 - Kinam Kim:
1.1 Silicon technologies and solutions for the data-driven world. 1-7 - Sehat Sutardja:
1.2 The future of IC design innovation. 1-6 - Willy Sansen:
1.3 Analog CMOS from 5 micrometer to 5 nanometer. 1-6 - Ehsan Afshari, Minoru Fujishima:
Session 2 Overview: RF TX/RX design techniques: RF subcommittee. 28-29 - Hao Wu, Mohyee Mikhemar, David Murphy, Hooman Darabi, Mau-Chung Frank Chang
:
2.1 A highly linear inductorless wideband receiver with phase- and thermal-noise cancellation. 1-3 - Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. 1-3 - Fanyi Meng, Kaixue Ma, Kiat Seng Yeo:
2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS. 1-3 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF. 1-3 - Wanxin Ye, Kaixue Ma, Kiat Seng Yeo:
2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM. 1-3 - Ahmed Farouk Aref, Renato Negra, Muhammad Abdullah Khan:
2.6 Class-0: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications. 1-3 - Seung-Chul Lee, Ji-Seon Paek, Jun-Hee Jung, Yong-Sik Youn, Sung-Jun Lee, Min-Soo Cho, Jae-Jol Han, Jung-Hyun Choi, Yong-Whan Joo, Takahiro Nomiyama, Su-Ho Lee, Il-Young Sohn, Thomas Byunghak Cho, Byeong-Ha Park, Inyup Kang:
2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power. 1-3 - Song Hu, Shouhei Kousai, Hua Wang:
2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement. 1-3 - Kunal Datta, Hossein Hashemi:
2.9 A 29dBm 18.5% peak PAE mm-Wave digital power amplifier with dynamic load modulation. 1-3 - Aurelien Larie, Eric Kerherve, Baudouin Martineau, Lionel Vogt, Didier Belot:
2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC. 1-3 - Ken Chang, Shunichi Kaeriyama:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee. 50-51 - Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Kambiz Vakilian, Anthony Brewster:
3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS. 1-3 - Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. 1-3 - Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang:
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. 1-3 - Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. 1-3 - Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. 1-3 - Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS. 1-3 - Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. 1-3 - Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu:
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. 1-3 - Atsuki Inoue, Jinuk Luke Shin:
Session 4 overview: Processors: High-performance digital subcommittee. 68-69 - James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake:
4.1 22nm Next-generation IBM System z microprocessor. 1-3 - Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. 1-3 - Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang:
4.3 Fine-grained adaptive power management of the SPARC M7 processor. 1-3 - Ronald P. Luijten, Dae Pham, Rolf Clauberg, Matteo Cossale, Huy N. Nguyen, Mihir Pandya:
4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density. 1-3 - William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family. 1-3 - Seongwook Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications. 1-3 - Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. 1-3 - Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White:
4.8 A 28nm x86 APU optimized for power and area efficiency. 1-3 - Xicheng Jiang, Ed van Tuijl:
Session 5 overview: Analog techniques: Analog subcommittee. 86-87 - Yoshinori Kusuda:
5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming. 1-3 - Long Xu, Burak Gonen, Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
5.2 A 110dB SNR ADC with ±30V input common-mode range and 8μV Offset for current sensing applications. 1-3 - Yi-Lin Tsai, Feng-Wen Lee, Tzu-Ying Chen, Tsung-Hsien Lin:
5.3 A 2-channel -83.2dB crosstalk 0.061mm2 CCIA with an orthogonal frequency chopping technique. 1-3 - Aatmesh Shrivastava, Kyle Craig, Nathan E. Roberts, David D. Wentzloff, Benton H. Calhoun:
5.4 A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems. 1-3 - Joeri Lechevallier, Remko E. Struiksma, Hani Sherry, Andreia Cathelin, Eric A. M. Klumperink, Bram Nauta:
5.5 A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply. 1-3 - Saad Bin Nasir, Samantak Gangopadhyay, Arijit Raychowdhury:
5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. 1-3 - Jongmi Lee, Youngwoo Ji, Seungnam Choi, Young-Chul Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.7 A 29nW bandgap reference circuit. 1-3 - Gerhard Maderbacher, Stefano Marsili, Mario Motz, Thomas Jackum, Johannes Thielmann, Henrik Hassander, Herbert Gruber, Florian Hus, Christoph Sandner:
5.8 A digitally assisted single-point-calibration CMOS bandgap voltage reference with a 3σ inaccuracy of ±0.08% for fuel-gauge applications. 1-3 - Danielle Griffith, James Murdock, Per Torstein Røine, Thomas Murphy:
5.9 A 37μW dual-mode crystal oscillator for single-crystal radios. 1-3 - Junghyup Lee, Pyoungwon Park, SeongHwan Cho, Minkyu Je:
5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. 1-3 - Yusuke Oike, Young-Sun Na:
Session 6 overview: Image sensors and displays: IMMD subcommittee. 108-109 - Atsushi Suzuki, Nobutaka Shimamura, Toshiki Kainuma, Naoki Kawazu, Chihiro Okada, Takumi Oka, Kensuke Koiso, Atsushi Masagaki, Yoichi Yagasaki, Shigeru Gonoi, Tatsuya Ichikawa, Masatoshi Mizuno, Tatsuya Sugioka, Takafumi Morikawa, Yoshiaki Inada, Hayato Wakabayashi:
6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications. 1-3 - Ryohei Funatsu, Steven Huang, Takayuki Yamashita, Kevin Stevulak, Jeff Rysinski, David Estrada, Shi Yan, Takuji Soeno, Tomohiro Nakamura, Tetsuya Hayashida, Hiroshi Shimamoto, Barmak Mansoorian:
6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs. 1-3 - Jaehyuk Choi, Jungsoon Shin, Dongwoo Kang, Du-Sik Park:
6.3 A 45.5μW 15fps always-on CMOS image sensor for mobile and wearable devices. 1-3 - Futa Mochizuki, Keiichiro Kagawa, Shin-ichiro Okihara, Min-Woong Seo, Bo Zhang, Taishi Takasawa, Keita Yasutomi, Shoji Kawahito:
6.4 Single-shot 200Mfps 5×3-aperture compressive CMOS imager. 1-3 - Takuro Ohmaru, Takashi Nakagawa, Shuhei Maeda, Yuki Okamoto, Munehiro Kozuma, Seiichi Yoneda, Hiroki Inoue, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Shunpei Yamazaki:
6.5 25.3μW at 60fps 240×160-pixel vision sensor for motion capturing with in-pixel non-volatile analog memory using crystalline oxide semiconductor FET. 1-3 - Mutsumi Hamaguchi, Michiaki Takeda, Masayuki Miyamoto:
6.6 A 240Hz-reporting-rate mutual-capacitance touch-sensing analog front-end enabling multiple active/passive styluses with 41dB/32dB SNR for 0.5mm diameter. 1-3 - Li Du, Yan Zhang, Frank Hsiao, Adrian Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang:
6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices. 1-3 - Changbyung Park, Sungsoo Park, Kiduk Kim, Sang-Hui Park, Juwan Park, Yunhee Huh, Byunghoon Kang, Gyu-Hyeong Cho:
6.8 A pen-pressure-sensitive capacitive touch system using electrically coupled resonance pen. 1-3 - Fatih Hamzaoglu, Takashi Kono:
Session 7 overview: Non-volatile memory solutions: Memory subcommittee. 126-127 - Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kouno, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, Masahiro Kamoshida, Masatoshi Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita:
7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. 1-3 - Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Ohsuk Kwon, Ji-Sang Lee, Moosung Kim, Sang-Hyun Joo, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. 1-3 - Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. 1-3 - Chankyung Kim, Keewon Kwon, Chulwoo Park, Sungjin Jang, Joosun Choi:
7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array. 1-3 - Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita:
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. 1-3 - Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seungwoo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj Rajagopal, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yongjin Kwon, Min-Jae Lee, Sunghoon Kim, Seunghoon Shin, Hyunggon Kim, Jin-Tae Kim, Ki-Sung Kim, Han-Sung Joo, Chanjin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. 1-3 - Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi:
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. 1-3 - Victor V. Zyuban, Peter Nilsson:
Session 8 overview: Low-power digital techniques: Energy-efficient digital. 142-143 - James Myers, Anand Savanth, David Howard, Rohan Gaddh, Pranay Prabhat, David Flynn:
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. 1-3 - Wootaek Lim, Inhee Lee, Dennis Sylvester, David T. Blaauw:
8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic. 1-3 - Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale:
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. 1-3 - Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester:
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. 1-3 - Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. 1-3 - Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. 1-3 - Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov:
8.7 Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm. 1-3 - Li Lin, Chun-Huat Heng:
Session 9 overview: High-performance wireless: Wireless subcommittee. 158-159 - Theodore Georgantas, Kostis Vavelidis, Nikos Haralabidis, Stamatis Bouras, Iason Vassiliou, Charalampos Kapnistis, Yiannis Kokolakis, Hamed Peyravi, Gerasimos Theodoratos, Konstantinos S. Vryssas, Nikos Kanakaris, Christos Kokozidis, Spyros Kavvadias, Sofoklis Plevridis, Paul Mudge, Igor Elgorriaga, Aris Kyranas, Spyridon Liolis, Eleni Kytonaki, Giorgos Konstantopoulos, Pavlos Robogiannakis, Kosmas Tsilipanos, Michael Margaras, Panagiotis Betzios, Rahul Magoon, Nias Bouras, Maryam Rofougaran, Reza Rofougaran:
9.1 A 13mm2 40nm multiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver. 1-3 - José Moreira, Stephan Leuschner, Nenad Stevanovic, Harald Pretl, Peter Pfann, Ronald Thüringer, Martin Kastner, Christian Proll, Andreas Schwarz, Florian Mrugalla, Jimena Saporiti, Umut Basaran, Andreas Langer, Tobias D. Werth, Timo Gossmann, Boris Kapfelsperger, Johann Pletzer:
9.2 A single-chip HSPA transceiver with fully integrated 3G CMOS power amplifiers. 1-3 - Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. 1-3 - Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin:
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio. 1-3 - Hadong Jin, Dongsu Kim, Sangsu Jin, Hankyu Lee, Kyunghoon Moon, Huijung Kim, Bumman Kim:
9.5 efficient digital quadrature transmitter based on IQ cell sharing. 1-3 - Elbert Bechthum, Georgi I. Radulov, Joost Briaire, Govert Geelen, Arthur H. M. van Roermund:
9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz. 1-3 - Yen-Horng Chen, Neric Fong, Bing Xu, Caiyi Wang:
9.7 An LTE SAW-less transmitter using 33% duty-cycle LO signals for harmonic suppression. 1-3 - Gerrit den Besten, Ajith Amerasekera:
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. 174-175 - Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda:
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. 1-3 - Wouter Volkaerts, Niels Van Thienen, Patrick Reynaert:
10.2 An FSK plastic waveguide communication link in 40nm CMOS. 1-3 - Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. 1-3 - Hyun-Wook Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Bai-Sun Kong, Young-Hyun Jun:
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface. 1-3 - Rajeev K. Dokania, Alexandra M. Kern, Mike He, Adam C. Faust, Richard Tseng, Skyler Weaver, Kai Yu, Christiaan Bil, Tao Liang, Frank O'Mahony:
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. 1-3 - Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu:
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. 1-3 - Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. 1-3 - Che-Fu Liang, Ping-Ying Wang:
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. 1-3 - Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. 1-3 - Sam Kavusi, Makoto Ikeda:
Session 11 overview: Sensors and imagers for life sciences: IMMD subcommittee. 194-195 - JongKwan Choi, Jae-Myoung Kim, Gunpil Hwang, Jaehyeok Yang, MinGyu Choi, Hyeon-Min Bae:
11.1 A time-divided spread-spectrum code based 15pW-detectable multi-channel fNIRS IC for portable functional brain imaging. 1-3 - Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Taishi Takasawa, Yoshimasa Kawata, Nobukazu Teranishi, Zhuo Li, Izhal Abdul Halin, Shoji Kawahito:
11.2 A 10.8ps-time-resolution 256×512 image sensor with 2-Tap true-CDS lock-in pixels for fluorescence lifetime imaging. 1-3 - Matteo Perenzoni, Nicola Massari, Daniele Perenzoni, Leonardo Gasparini, David Stoppa:
11.3 A 160×120-pixel analog-counting single-photon imager with Sub-ns time-gating and self-referenced column-parallel A/D conversion for fluorescence lifetime imaging. 1-3 - Augusto Carimatto, Shingo Mandai, Esteban Venialgo, Ting Gong, Giacomo Borghi, Dennis R. Schaart, Edoardo Charbon:
11.4 A 67, 392-SPAD PVTB-compensated multi-channel digital SiPM with 432 column-parallel 48ps 17b TDCs for endoscopic time-of-flight PET. 1-3 - Neale A. W. Dutton, Salvatore Gnecchi, Luca Parmesan, Andrew J. Holmes, Bruce Rae, Lindsay A. Grant, Robert K. Henderson:
11.5 A time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter. 1-3 - Kian Ann Ng, Yong Ping Xu:
11.6 A multi-channel neural-recording amplifier system with 90dB CMRR employing CMOS-inverter-based OTAs with CMFB through supply rails in 65nm CMOS. 1-3 - Jong Seok Park, Taiyun Chi, Jessica Butts, Tracy Hookway, Todd C. McDevitt, Hua Wang:
11.7 A multimodality CMOS sensor array for cell-based assay and drug screening. 1-3 - Hao-Yen Tang, Yipeng Lu, Stephanie Fung, David A. Horsley, Bernhard E. Boser:
11.8 Integrated ultrasonic system for measuring body-fat composition. 1-3 - Makato Takamiya, Dragan Maksimovic:
Session 12 overview: Inductor-based power conversion: Analog subcommittee. 212-213 - Sang-Han Lee, Jun-Suk Bang, Kye-Seok Yoon, Sung-Wan Hong, Changsik Shin, Min-Yong Jung, Gyu-Hyeong Cho:
12.1 A 0.518mm2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS. 1-3 - Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. 1-3 - Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems. 1-3 - Stefan Dietrich, Sebastian Strache, Bastian Mohr, Jan Henning Mueller, Leo Rolff, Ralf Wunderlich, Stefan Heinen:
12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology. 1-3 - Min-Yong Jung, Sang-Hui Park, Jun-Suk Bang, Dong-Chul Park, Se-un Shin, Gyu-Hyeong Cho:
12.5 An error-based controlled single-inductor 10-output DC-DC buck converter with high efficiency at light load using adaptive pulse modulation. 1-3 - Yi-Ping Su, Chiun-He Lin, Shen-Yu Peng, Ru-Yu Huang, Te-Fu Yang, Shin-Hao Chen, Ting-Jung Lo, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai:
12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control. 1-3 - Mehdi Kiani, Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo:
12.7 A power-management ASIC with Q-modulation capability for efficient inductive power transmission. 1-3 - Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications. 1-3 - Kyung-Goo Moti, Filippo Neri, Sungwoo Moon, Pyeongwoo Yeon, Jinhyuck Yu, Youso Cheon, Yong-Seong Roh, Myeonglyong Ko, Byeong-Ha Park:
12.9 A fully integrated 6W wireless power receiver operating at 6.78MHz with magnetic resonance coupling. 1-3 - Ali Afsahi, Jan van Sinderen:
Session 13 overview: Energy-efficient RF systems: RF & wireless subcommittees. 232-233 - Jae-Seung Lee, Joo-Myoung Kim, Jaesup Lee, Seok-Kyun Han, Sang-Gug Lee:
13.1 A 227pJ/b -83dBm 2.4GHz multi-channel OOK receiver adopting receiver-based FLL. 1-3 - Yao-Hong Liu, Christian Bachmann, Xiaoyan Wang, Yan Zhang, Ao Ba, Benjamin Busze, Ming Ding, Pieter Harpe, Gert-Jan van Schaik, Georgios N. Selimis, Hans Giesen, Jordy Gloudemans, Adnane Sbai, Li Huang, Hiromu Kato, Guido Dolmans, Kathleen Philips, Harmke de Groot:
13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS. 1-3 - Jan Prummel, Michail Papamichail, Michele Ancis, John Willms, Rahul Todi, William Aartsen, Wim Kruiskamp, Johan Haanstra, Enno Opbroek, Soren Rievers, Peter Seesink, Harrie Woering, Chris Smit:
13.3 A 10mW Bluetooth Low-Energy transceiver with on-chip matching. 1-3 - Tomohiro Sano, Masakazu Mizokami, Hiroaki Matsui, Keisuke Ueda, Kenichi Shibata, Kenji Toyota, Tatsuhito Saitou, Hisayasu Sato, Koichi Yahagi, Yoshihiro Hayashi:
13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network. 1-3 - Camilo Salazar, Andreas Kaiser, Andreia Cathelin, Jan M. Rabaey:
13.5 A -97dBm-sensitivity interferer-resilient 2.4GHz wake-up receiver using dual-IF multi-N-Path architecture in 65nm CMOS. 1-3 - Anith Selvakumar, Meysam Zargham, Antonio Liscidini:
13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology. 1-3 - Arun Paidimarri, Nathan Ickes, Anantha P. Chandrakasan:
13.7 A +10dBm 2.4GHz transmitter with sub-400pW leakage and 43.7% system efficiency. 1-3 - Atsushi Shirane, Haowei Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique. 1-3 - Anthony Hill, Hiroo Hayashi:
Session 14 overview: Digital PLLs and SoC building blocks: High-performance digital subcommittee. 250-251 - Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. 1-3 - Kaiyuan Yang, Qing Dong, David T. Blaauw, Dennis Sylvester:
14.2 A physically unclonable function with BER-8 for robust chip authentication using oscillator collapse in 40nm CMOS. 1-3 - Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto:
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm. 1-3 - Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho:
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. 1-3 - Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski:
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. 1-3 - Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull:
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster. 1-3 - Teng Yang, Doyun Kim, Peter R. Kinget, Mingoo Seok:
14.7 In-situ techniques for in-field sensing of NBTI degradation in an SRAM register file. 1-3 - Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park:
14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. 1-3 - Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang:
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. 1-3 - Seung-Tak Ryu, Matt Straayer:
Session 15 overview: Data-converter techniques: Data converters subcommittee. 270-271 - Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. 1-3 - Chen-Yen Ho, Cong Liu, Chi-Lun Lo, Hung-Chieh Tsai, Tze-Chien Wang, Yu-Hsin Lin:
15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation. 1-3 - Hugo Westerveld, Daniël Schinkel, Ed van Tuijl:
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise. 1-3 - Maoqiang Liu, Pieter Harpe, Rainier van Dommele, Arthur H. M. van Roermund:
15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation. 1-3 - Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park:
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. 1-3 - Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee:
15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers. 1-3 - Martin Kramer, Erwin Janssen, Kostas Doris, Boris Murmann:
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS. 1-3 - Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Jesse Coulon, Jake Hu, David Smith, Paul E. Landman, Mark Weaver:
15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC. 1-3 - Jan Genoe, Koichi Nose:
Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee. 288-289 - Yigit Mahsereci, Stefan Saller, Harald Richter, Joachim N. Burghartz:
16.1 An ultra-thin flexible CMOS stress sensor demonstrated on an adaptive robotic gripper. 1-3 - Warren Rieutort-Louis, Tiffany Moy, Zhuo Wang, Sigurd Wagner, James C. Sturm, Naveen Verma:
16.2 A large-area image sensing and detection system based on embedded thin-film classifiers. 1-3 - Kris Myny, Brian Cobb, Jan-Laurens P. J. van der Steen, Ashutosh Tripathi, Jan Genoe, Gerwin H. Gelinck, Paul Heremans:
16.3 Flexible thin-film NFC tags powered by commercial USB reader device at 13.56MHz. 1-3 - Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. 1-3 - Nicolas Delorme, Christophe Le Blanc, Alessandro Dezzani, Mickael Bely, Alexandre Ferret, Simon Laminette, Jerome Roudier, Éric Colinet:
16.5 A NEMS-array control IC for sub-attogram gravimetric sensing applications in 28nm CMOS technology. 1-3 - Jinhong Ahn, Jeaheung Lim, Seok-Hyang Kim, Jun-Yeon Yun, Changhyun Kim, Sang-Hoon Hong, Myoung-Jin Lee, Youngjune Park:
16.6 Double-side CMOS-CNT biosensor array with padless structure for simple bare-die measurements in a medical environment. 1-3 - Minkyu Song, Lei Chen, Joseph Sankman, Stephen Terry, Dongsheng Ma:
16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time. 1-3 - Bichoy W. Bahr, Laura C. Popa, Dana Weinstein:
16.8 1GHz GaN-MMIC monolithically integrated MEMS-based oscillators. 1-3 - Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. 1-3 - Leland Chang, Takefumi Yoshikawa:
Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee. 308-309 - Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang:
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. 1-3 - Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang:
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. 1-3 - Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Hiroyuki Yamauchi:
17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme. 1-3 - Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns:
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. 1-3 - Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku:
17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. 1-3 - Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim:
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. 1-3 - Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok-Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung-Hwan Choi, Seong-Jin Jang, Joo-Sun Choi:
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs. 1-3 - Mike Polley, Paul Liang:
Session 18 overview: SoCs for mobile vision, sensing, and communications: Energy-efficient digital subcommittee. 324-325 - Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Seongwook Park, Kyuho Lee, Youchang Kim, Hoi-Jun Yoo:
18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications. 1-3 - Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori:
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. 1-3 - Youchang Kim, Injoon Hong, Hoi-Jun Yoo:
18.3 A 0.5V 54μW ultra-low-power recognition processor with 93.5% accuracy geometric vocabulary tree and 47.5% database compression. 1-3 - Jintao Zhang, Zhuo Wang, Naveen Verma:
18.4 A matrix-multiplying ADC implementing a machine-learning classifier directly with data conversion. 1-3 - Fengbo Ren, Dejan Markovic:
18.5 A configurable 12-to-237KS/s 12.8mW sparse-approximation engine for mobile ExG data aggregation. 1-3 - Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Fu-Chun Yeh, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Ryan Chen, H. Y. Hsu, Kevin Jou:
18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications. 1-3 - Chia-Hsiang Chen, Wei Tang, Zhengya Zhang:
18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. 1-3 - Stefano Pellerano, Koji Takinami:
Session 19 overview: Advanced wireless techniques: Wireless subcommittee. 340-341 - Jin Zhou, Tsung-Hao Chuang, Tolga Dinc, Harish Krishnaswamy:
19.1 Receiver with >20MHz bandwidth self-interference cancellation suitable for FDD, co-existence and full-duplex applications. 1-3 - Dirk-Jan van den Broek, Eric A. M. Klumperink, Bram Nauta:
19.2 A self-interference-cancelling receiver for in-band full-duplex wireless with low distortion under cancellation of strong TX leakage. 1-3 - Run Chen, Hossein Hashemi:
19.3 Reconfigurable SDR receiver with enhanced front-end frequency selectivity suitable for intra-band and inter-band carrier aggregation. 1-3 - Rabia Tugce Yazicigil, Tanbir Haque, Michael R. Whalen, Jeffrey Yuan, John Wright, Peter R. Kinget:
19.4 A 2.7-to-3.7GHz rapid interférer detector exploiting compressed sampling with a quadrature analog-to-information converter. 1-3 - Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
19.5 An HCI-healing 60GHz CMOS transceiver. 1-3 - Hong Gul Han, Byung-Gyu Yu, Tae Wook Kim:
19.6 A 1.9mm-precision 20GS/S real-time sampling receiver using time-extension method for indoor localization. 1-3 - Davide Guermandi, Qixian Shi, Alaa Medra, Tomohiro Murata, Wim Van Thillo, André Bourdoux, Piet Wambacq, Vito Giannini:
19.7 A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS. 1-3 - Makoto Nagata, Stefano Stanzione:
Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee. 356-357 - Hans Meyvaert, Gerard Villar Piqué, Ravi Karadi, Henk Jan Bergveld, Michiel Steyaert:
20.1 A light-load-efficient 11/1 switched-capacitor DC-DC converter with 94.7% efficiency while delivering 100mW at 3.3V. 1-3 - Christopher Schaef, Kapil Kesarwani, Jason T. Stauth:
20.2 A variable-conversion-ratio 3-phase resonant switched capacitor converter with 85% efficiency at 0.91W/mm2 using 1.1nH PCB-trace inductors. 1-3 - Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese:
20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. 1-3 - Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. 1-3 - Junmin Jiang, Yan Lu, Cheng Huang, Wing-Hung Ki, Philip K. T. Mok:
20.5 A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement. 1-3 - Joachim Leicht, Mohammad Amayreh, Christian Moranz, Dominic Maurath, Thorsten Hehn, Yiannos Marioli:
20.6 Electromagnetic vibration energy harvester interface IC with conduction-angle-controlled maximum-power-point tracking and harvesting efficiencies of up to 90%. 1-3 - Xiaosen Liu, Edgar Sánchez-Sinencio:
20.7 A 0.45-to-3V reconfigurable charge-pump energy harvester with two-dimensional MPPT for Internet of Things. 1-3 - Stefano Stanzione, Chris van Liempd, Misato Nabeto, Refet Firat Yazicioglu, Chris Van Hoof:
20.8 A 500nW batteryless integrated electrostatic energy harvester interface based on a DC-DC converter with 60V maximum input voltage and operating from 1μW available power, including MPPT and cold start. 1-3 - Hsuan-Ju Chen, Yi-Hsiang Wang, Peng-Chang Huang, Tai-Haur Kuo:
20.9 An energy-recycling three-switch single-inductor dual-input buck/boost DC-DC converter with 93% peak conversion efficiency and 0.5mm2 active area for light energy harvesting. 1-3 - Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin:
20.10 A 50nW-to-10mW output power tri-mode digital buck converter with self-tracking zero current detection for photovoltaic energy harvesting. 1-3 - David Ruffieux, Antoine Dupret:
Session 21 overview: Innovative personalized biomédical systems: Technology directions subcommittee. 378-379 - Hyunwoo Cho, Hyunki Kim, Minseo Kim, Jaeeun Jang, Joonsung Bae, Hoi-Jun Yoo:
21.1 A 79pJ/b 80Mb/s full-duplex transceiver and a 42.5μW 100kb/s super-regenerative transceiver for body channel communication. 1-3 - Pieter Harpe, Hao Gao, Rainier van Dommele, Eugenio Cantatore, Arthur H. M. van Roermund:
21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC. 1-3 - Alicia Klinefelter, Nathan E. Roberts, Yousef Shakhsheer, Patricia González, Aatmesh Shrivastava, Abhishek Roy, Kyle Craig, Muhammad Faisal, James Boley, Seunghyun Oh, Yanqing Zhang, Divya Akella, David D. Wentzloff, Benton H. Calhoun:
21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios. 1-3 - Mehran Bakhshiani, Michael A. Suster, Pedram Mohseni:
21.4 A microfluidic-CMOS platform with 3D capacitive sensor and fully integrated transceiver IC for palmtop dielectric spectroscopy. 1-3 - Te-Hsuen Tzeng, Chun-Yen Kuo, San-Yuan Wang, Po-Kai Huang, Po-Hung Kuo, Yen-Ming Huang, Wei-Che Hsieh, Shih-An Yu, Yufeng Jane Tseng, Wei-Cheng Tian, Si-Chen Lee, Shey-Shi Lu:
21.5 A portable micro gas chromatography system for volatile compounds detection with 15ppb of sensitivity. 1-3 - Po-Hung Kuo, Jui-Chang Kuo, Hsiao-Ting Hsueh, Jian-Yu Hsieh, Yi-Chun Huang, Tao Wang, Yen-Hung Lin, Chih-Ting Lin, Yao-Joe Yang, Shey-Shi Lu:
21.6 A smart CMOS assay SoC for rapid blood screening test of risk prediction. 1-3 - Achille Donida, Giuseppe Di Dato, Paolo Cunzolo, Marco Sala, Filippo Piffaretti, Paolo Orsatti, Diego Barrettino:
21.7 A 0.036mbar circadian and cardiac intraocular pressure sensor for smart implantable lens. 1-3 - Muhammad Awais Bin Altaf, Chen Zhang, Jerald Yoo:
21.8 A 16-ch patient-specific seizure onset and termination detection SoC with machine-learning and voltage-mode transcranial stimulation. 1-3 - Unsoo Ha, Yongsu Lee, Hyunki Kim, Taehwan Roh, Joonsung Bae, Changhyeon Kim, Hoi-Jun Yoo:
21.9 A wearable EEG-HEG-HRV multimodal system with real-time tES monitoring for mental health management. 1-3 - Azita Emami, Hyeon-Min Bae:
Session 22 overview: High-speed optical links: Wireline subcommittee. 398-399 - Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli:
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. 1-3 - Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. 1-3 - Mayank Raj, Saman Saeedi, Azita Emami:
22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS. 1-3 - Kunzhi Yu, Hao Li, Cheng Li, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo:
22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization. 1-3 - Michal Rakowski, Marianna Pantouvaki, Peter De Heyn, Peter Verheyen, Mark Ingels, Hongtao Chen, Jeroen De Coster, Guy Lepage, Brad Snyder, Kristin De Meyer, Michiel Steyaert, Nicola Pavarelli, Jun Su Lee, Peter O'Brien, Philippe P. Absil, Joris Van Campenhout:
22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver. 1-3 - Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang:
22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. 1-3 - Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura:
22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. 1-3 - Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura:
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. 1-3 - Marco Cignoli, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Enrico Temporiti, Francesco Svelto:
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s. 1-3 - Andy Charnas, Youngmin Shin:
Session 23 overview: Low-power SoCs: High-performance digital subcommittee. 418-419 - Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park:
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor. 1-3 - Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen:
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications. 1-3 - Hugh Mair, Gordon Gammie, Alice Wang, Sumanth Gururajarao, Ichiro Lin, HsinChen Chen, Wuan Kuo, Anand Rajagopalan, Wei-Zheng Ge, Rolf Lagerquist, Syed Rahman, C. J. Chung, Simon Wang, Lee-Kee Wong, Yi-Chang Zhuang, Kent Li, Jidong Wang, Minh Chau, Yijing Liu, Daniel Dia, Mark Peng, Uming Ko:
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. 1-3 - Chris J. Nicol, Shinichiro Mutoh:
Session 24 overview: Secure, efficient circuits for IoT: Technology directions subcommittee. 426-427 - Ingrid Verbauwhede, Josep Balasch, Sujoy Sinha Roy, Anthony Van Herrewege:
24.1 Circuit challenges from cryptography. 1-2 - Komail M. H. Badami, Steven Lauwereins, Wannes Meert, Marian Verhelst:
24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector. 1-3 - Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. 1-3 - Atsutake Kosuge, Shu Ishizuka, Marni Abe, Satoshi Ichikawa, Tadahiro Kuroda:
24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. 1-3 - Payam Heydari, Taizo Yamawaki:
Session 25 overview: RF frequency generation from GHz to THz: RF subcommittee. 436-437 - Colin Weltin-Wu, Guobi Zhao, Ian Galton:
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. 1-3 - Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. 1-3 - David Murphy, Hooman Darabi, Hao Wu:
25.3 A VCO with implicit common-mode resonance. 1-3 - Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski:
25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators. 1-3 - Ruonan Han, Chen Jiang, Ali Mostajeran, Mohammad Emadi, Hamidreza Aghasi, Hani Sherry, Andreia Cathelin, Ehsan Afshari:
25.5 A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems. 1-3 - Zhiqiang Huang, Howard Cam Luong, Baoyong Chi, Zhihua Wang, Haikun Jia:
25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter. 1-3 - Long Kong, Behzad Razavi:
25.7 A 2.4GHz 4mW inductorless RF synthesizer. 1-3 - Ali Mostajeran, Mehrdad Sharif Bakhtiar, Ehsan Afshari:
25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz offset frequencies in 0.13μm CMOS using an ISF manipulation technique. 1-3 - Kannan A. Sankaragomathi, Jabeom Koo, Richard C. Ruby, Brian P. Otis:
25.9 A ±3ppm 1.1mW FBAR frequency reference with 750MHz output and 750mV supply. 1-3 - Hae-Seung Lee, Seng-Pan Li:
Session 26 overview: Nyquist-rate converters: Data converters subcommittee. 456-457 - Yong Lim, Michael P. Flynn:
26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC. 1-3 - Ming Ding, Pieter Harpe, Yao-Hong Liu, Benjamin Busze, Kathleen Philips, Harmke de Groot:
26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. 1-3 - Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult:
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. 1-3 - Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. 1-3 - Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. 1-3 - Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen:
26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS. 1-3 - Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. 1-3 - Ralf Brederlow, Michiel A. P. Pertijs:
Session 27 overview: Physical sensors: Imagers, MEMS, medical and displays subcommittee. 472-473 - Ganesh K. Balachandran, Vladimir P. Petkov, Thomas Mayer, Thorsten Baislink:
27.1 A 3-Axis gyroscope for electronic stability control with continuous self-test. 1-3 - Xi Wang, Jian Zhao, Yang Zhao, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu:
27.2 A1.2μg/√Hz-resolution 0.4μg-bias-instability MEMS silicon oscillating accelerometer with CMOS readout circuit. 1-3 - Chinwuba D. Ezekwe, Wolfram Geiger, Torsten Ohms:
27.3 A 3-axis open-loop gyroscope with demodulation phase error correction. 1-3 - Manohar Nagaraju, Andrew Lingley, Suresh Sridharan, Jingren Gu, Richard C. Ruby, Brian P. Otis:
27.4 A 0.8mm3 ±0.68psi single-chip wireless pressure sensor for TPMS applications. 1-3 - Hui Jiang, Zu-yao Chang, Michiel A. P. Pertijs:
27.5 A 30ppm <80nJ ring-down-based readout circuit for resonant sensors. 1-3 - Wanyeong Jung, Seokhyeon Jeong, Sechang Oh, Dennis Sylvester, David T. Blaauw:
27.6 A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge. 1-3 - Yuming He, Zu-yao Chang, Lukasz S. Pakula, Saleh Heidary Shalmany, Michiel A. P. Pertijs:
27.7 A 0.05mm2 1V capacitance-to-digital converter based on period modulation. 1-3 - Rui Quan, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa:
27.8 A 4600μm2 1.5°C (3σ) 0.9kS/s thermal-diffusivity temperature sensor with VCO-based readout. 1-3 - Mahdi Kashmiri, Wilko J. Kindt, Frerik Witte, Robin Kearey, Daniel Carbonell:
27.9 A 200kS/s 13.5b integrated-fluxgate differential-magnetic-to-digital converter with an oversampling compensation loop for contactless current sensing. 1-3 - Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori:
F1: High-speed interleaved ADCs. 1-2 - Jonathan Chang, Leland Chang, Antoine Dupret, Chulwoo Kim, Fatih Hamzaoglu, Takefumi Yoshikawa:
F2: Memory trends: From big data to wearable devices. 1-2 - Marco Berkhout, Anton Bakker, Christoph Sandner, Wentai Liu, Chin-Ming Hung, Bill Redman-White:
F3: Cutting the last wire - Advances in wireless power. 1-2 - Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose:
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels. 1-2 - Piet Wambacq, Stefano Pellerano, Sven Mattisson, Shouhei Kousai, Ali Afsahi, Taizo Yamawaki:
F5: Advanced RF CMOS transmitter techniques. 1-2 - Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr:
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. 1-2 - Firat Yazicioglu, Peng Cong, Shahriar Mirabbasi:
ES2: Brain-machine interfaces: Integrated circuits talking to neurons. 1 - Bing Sheu, Kathy Wilcox, Ali M. Keshavarzi, Dimitri A. Antoniadis:
EP1: Moore's law challenges below 10nm: Technology, design and economic implications. 1 - Tsung-Hsien Lin, Carlo Samori, Richard Schreier:
EP2: Lost art? Analog tricks and techniques from the masters. 1 - Jack Kenney, Frank O'Mahony:
EP3: Innovating on the tapeout treadmill. 1 - Eric A. M. Klumperink, Sven Mattisson, Vojkan Vidojkovic:
ES3: How to achieve 1000× more wireless data capacity? 5G? 1 - Wim Dehaene:
SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages. 1-2
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