<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/isscc/TsaiYCLLS15" mdate="2019-06-02">
<author>Tsung-Hsien Tsai</author>
<author>Min-Shueh Yuan</author>
<author>Chih-Hsien Chang</author>
<author>Chia-Chun Liao</author>
<author>Chao-Chieh Li</author>
<author orcid="0000-0001-9848-1129">Robert Bogdan Staszewski</author>
<title>14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.</title>
<pages>1-3</pages>
<year>2015</year>
<booktitle>ISSCC</booktitle>
<ee>https://doi.org/10.1109/ISSCC.2015.7063025</ee>
<ee>https://www.wikidata.org/entity/Q58929553</ee>
<crossref>conf/isscc/2015</crossref>
<url>db/conf/isscc/isscc2015.html#TsaiYCLLS15</url>
</inproceedings></dblp>
