{"id":"https://openalex.org/W2280936279","doi":"https://doi.org/10.1109/hipc.2015.33","title":"Throughput Regulation in Shared Memory Multicore Processors","display_name":"Throughput Regulation in Shared Memory Multicore Processors","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2280936279","doi":"https://doi.org/10.1109/hipc.2015.33","mag":"2280936279"},"language":"en","primary_location":{"id":"doi:10.1109/hipc.2015.33","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hipc.2015.33","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 22nd International Conference on High Performance Computing (HiPC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077106442","display_name":"X. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"X. Chen","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115076591","display_name":"H. Xiao","orcid":"https://orcid.org/0009-0003-9644-3374"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Xiao","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025200449","display_name":"Y. Wardi","orcid":"https://orcid.org/0000-0001-5293-0478"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Wardi","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113186725","display_name":"S. Yalamanchili","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Yalamanchili","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5077106442"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":1.9379,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.86572948,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"12","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.8266479969024658},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.8083120584487915},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.789508581161499},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5792249441146851},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.5612772703170776},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4799109399318695},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4654479920864105},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4325600564479828},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42757830023765564},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41913729906082153},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10965362191200256},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09802958369255066},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08667540550231934}],"concepts":[{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.8266479969024658},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.8083120584487915},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.789508581161499},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5792249441146851},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.5612772703170776},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4799109399318695},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4654479920864105},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4325600564479828},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42757830023765564},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41913729906082153},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10965362191200256},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09802958369255066},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08667540550231934},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hipc.2015.33","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hipc.2015.33","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 22nd International Conference on High Performance Computing (HiPC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1587663028","https://openalex.org/W1600369258","https://openalex.org/W1965052050","https://openalex.org/W1981181124","https://openalex.org/W2010552195","https://openalex.org/W2013476156","https://openalex.org/W2046574526","https://openalex.org/W2050481923","https://openalex.org/W2052783747","https://openalex.org/W2079191345","https://openalex.org/W2086202544","https://openalex.org/W2090678868","https://openalex.org/W2094477153","https://openalex.org/W2099951182","https://openalex.org/W2112393996","https://openalex.org/W2116175063","https://openalex.org/W2118039752","https://openalex.org/W2133984922","https://openalex.org/W2143324466","https://openalex.org/W2145021036","https://openalex.org/W2237841525","https://openalex.org/W2509841691","https://openalex.org/W4238549726","https://openalex.org/W6677377052","https://openalex.org/W6820157634"],"related_works":["https://openalex.org/W2154351074","https://openalex.org/W2151223307","https://openalex.org/W2023400509","https://openalex.org/W2332054630","https://openalex.org/W2590100594","https://openalex.org/W2898122376","https://openalex.org/W2167303720","https://openalex.org/W2133682266","https://openalex.org/W2497617944","https://openalex.org/W1563139915"],"abstract_inverted_index":{"Performance":[0,124],"scaling":[1,6],"is":[2,18,43,61,73],"now":[3],"synonymous":[4],"with":[5,25],"the":[7,13,19,65,82,86,111,114,129],"number":[8],"of":[9,12,15,22,48,67,81,113],"cores.":[10,70],"One":[11],"consequences":[14],"this":[16,32,34],"shift":[17],"increasing":[20],"difficulty":[21],"designing":[23],"processors":[24],"predictable":[26],"and":[27,100,104,120],"controllable":[28],"performance.":[29],"To":[30],"address":[31],"challenge":[33],"paper":[35],"proposes":[36],"a":[37,132],"chip-scale":[38],"throughput":[39,66,84,91],"regulation":[40,92],"technique":[41],"that":[42],"based":[44,75],"on":[45,76,117],"dynamic":[46],"tracking":[47],"instruction":[49,101],"execution":[50],"dynamics":[51],"in":[52],"each":[53],"core.":[54],"A":[55],"new":[56],"variable":[57],"gain":[58,72],"controller":[59],"design":[60],"developed":[62],"for":[63,128],"regulating":[64],"modern":[68],"out-of-order":[69],"The":[71],"adjusted":[74],"an":[77],"on-line":[78],"sensitivity":[79],"analysis":[80],"core's":[83],"to":[85,131],"control":[87,95],"parameter.":[88],"We":[89],"explore":[90],"using":[93],"two":[94],"paramaters":[96],"-":[97],"core":[98],"frequency":[99],"issue":[102],"width":[103],"demonstrate":[105],"via":[106],"cycle-level,":[107],"full":[108],"system":[109],"simulation":[110],"utility":[112],"proposed":[115],"regulator":[116],"both":[118],"compute":[119],"memory":[121],"intensive":[122],"workloads.":[123],"results":[125],"are":[126],"presented":[127],"application":[130],"16":[133],"core,":[134],"cache":[135],"coherent":[136],"3D":[137],"multicore":[138],"processor.":[139]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
