{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:13:27Z","timestamp":1750306407931,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":35,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,9,28]],"date-time":"2015-09-28T00:00:00Z","timestamp":1443398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"DFG","award":["WU 245\/12-1, RA1889\/4-1"],"award-info":[{"award-number":["WU 245\/12-1, RA1889\/4-1"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,9,28]]},"DOI":"10.1145\/2786572.2788708","type":"proceedings-article","created":{"date-parts":[[2015,8,26]],"date-time":"2015-08-26T16:48:13Z","timestamp":1440607693000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Multi-Layer Test and Diagnosis for Dependable NoCs"],"prefix":"10.1145","author":[{"given":"Hans-Joachim","family":"Wunderlich","sequence":"first","affiliation":[{"name":"Computer Architecture, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart"}]},{"given":"Martin","family":"Radetzki","sequence":"additional","affiliation":[{"name":"Embedded Systems Engineering, University of Stuttgart, Pfaffenwaldring 5b, D-70569 Stuttgart"}]}],"member":"320","published-online":{"date-parts":[[2015,9,28]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429506"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024931"},{"volume-title":"Proc. of IEEE Int'l Test Conf. (ITC), 590--599","author":"Amory A.","key":"e_1_3_2_1_3_1","unstructured":"Amory , A. , Briao , E. , Cota , E. , Lubaszewski , M. , and Moraes , F . 2005. A scalable test strategy for network-on-chip routers . In Proc. of IEEE Int'l Test Conf. (ITC), 590--599 . Amory, A., Briao, E., Cota, E., Lubaszewski, M., and Moraes, F. 2005. A scalable test strategy for network-on-chip routers. In Proc. of IEEE Int'l Test Conf. (ITC), 590--599."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847907"},{"key":"e_1_3_2_1_5_1","unstructured":"Bushnell M. and Agrawal V.D. 2000. Essentials of electronic testing for digital memory and mixed-signal VLSI circuits. Chapters 7 & 8. Springer Science & Business Media.  Bushnell M. and Agrawal V.D. 2000. Essentials of electronic testing for digital memory and mixed-signal VLSI circuits. Chapters 7 & 8. Springer Science & Business Media."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.913755"},{"volume-title":"Proc. Design, Automation and Test in Europe (DATE), 1006--1011","author":"Corno F.","key":"e_1_3_2_1_7_1","unstructured":"Corno , F. , Cumani , G. , Sonza Reorda , M. , and Squillero , G . 2003. Fully automatic test program generation for microprocessor cores . In Proc. Design, Automation and Test in Europe (DATE), 1006--1011 . Corno, F., Cumani, G., Sonza Reorda, M., and Squillero, G. 2003. Fully automatic test program generation for microprocessor cores. In Proc. Design, Automation and Test in Europe (DATE), 1006--1011."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.27"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-012-5329-9"},{"volume-title":"Proc. 32nd IEEE VLSI Test Symposium (VTS), 1--6.","author":"Dalirsani A.","key":"e_1_3_2_1_10_1","unstructured":"Dalirsani , A. , Imhof , M.E. , and Wunderlich , H . -J. 2014. Structural Software-Based Self-Test of Network-on-Chip . In Proc. 32nd IEEE VLSI Test Symposium (VTS), 1--6. Dalirsani, A., Imhof, M.E., and Wunderlich, H.-J. 2014. Structural Software-Based Self-Test of Network-on-Chip. In Proc. 32nd IEEE VLSI Test Symposium (VTS), 1--6."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873662"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2013.150"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.22"},{"volume-title":"Proc. Design, Automation & Test in Europe (DATE), 1--6.","author":"Hosseinabady M.","key":"e_1_3_2_1_14_1","unstructured":"Hosseinabady , M. , Dalirsani , A. , and Navabi , Z . 2007. Using the inter- and intra-switch regularity in NoC switch testing . In Proc. Design, Automation & Test in Europe (DATE), 1--6. Hosseinabady, M., Dalirsani, A., and Navabi, Z. 2007. Using the inter- and intra-switch regularity in NoC switch testing. In Proc. Design, Automation & Test in Europe (DATE), 1--6."},{"volume-title":"Proc. IEEE Int'l Symp. On Circuits and Systems (ISCAS), 1770--1773","author":"Jantsch A.","key":"e_1_3_2_1_15_1","unstructured":"Jantsch , A. , Lauter , R. , and Vitkowski , A . 2005. Power analysis of link level and end-to-end data protection in networks on chip . In Proc. IEEE Int'l Symp. On Circuits and Systems (ISCAS), 1770--1773 . Jantsch, A., Lauter, R., and Vitkowski, A. 2005. Power analysis of link level and end-to-end data protection in networks on chip. In Proc. IEEE Int'l Symp. On Circuits and Systems (ISCAS), 1770--1773."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.202"},{"volume-title":"Reliable Communication by Fault-Tolerant Multilayer Routing. Master Thesis","author":"Kaufmann M.","key":"e_1_3_2_1_17_1","unstructured":"Kaufmann , M. 2012. Reliable Communication by Fault-Tolerant Multilayer Routing. Master Thesis , University of Stuttgart. Kaufmann, M. 2012. Reliable Communication by Fault-Tolerant Multilayer Routing. Master Thesis, University of Stuttgart."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048399"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.68"},{"volume-title":"Proc. 2nd Int'l Conf. on Nano-Networks (NanoNet), 1--5.","author":"Lehtonen T.","key":"e_1_3_2_1_20_1","unstructured":"Lehtonen , T. , Liljeberg , P. , and Plosila , J . 2007. Analysis of forward error correction methods for nanoscale networks-on-chip . In Proc. 2nd Int'l Conf. on Nano-Networks (NanoNet), 1--5. Lehtonen, T., Liljeberg, P., and Plosila, J. 2007. Analysis of forward error correction methods for nanoscale networks-on-chip. In Proc. 2nd Int'l Conf. on Nano-Networks (NanoNet), 1--5."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2013711"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.21"},{"volume-title":"Proc. 16th IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), 437--442","author":"Liu C.","key":"e_1_3_2_1_23_1","unstructured":"Liu , C. , Zhang , L. , Han , Y. , and Li , X . 2011. A resilient on-chip router design through data path salvaging . In Proc. 16th IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), 437--442 . Liu, C., Zhang, L., Han, Y., and Li, X. 2011. A resilient on-chip router design through data path salvaging. In Proc. 16th IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), 437--442."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839486(410) 24"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2522968.2522976"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.41"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.12"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2013.74"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2015.36"},{"volume-title":"Proc. Int'l Test Conference (ITC), 1--10","author":"Shamshiri S.","key":"e_1_3_2_1_30_1","unstructured":"Shamshiri , S. , Ghofrani , A. , and Cheng , K . -T. 2011. End-to-end error correction and online diagnosis for on-chip networks . In Proc. Int'l Test Conference (ITC), 1--10 . Shamshiri, S., Ghofrani, A., and Cheng, K.-T. 2011. End-to-end error correction and online diagnosis for on-chip networks. In Proc. Int'l Test Conference (ITC), 1--10."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2188801"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223600"},{"key":"e_1_3_2_1_33_1","unstructured":"Wunderlich H.-J. and Holst S. 2010. Generalized Fault Modeling for Logic Diagnosis. In Wunderlich H.-J.(Ed.) Models in Hardware Testing ISBN: 978-90-481-3281-2 Springer-Verlag Heidelberg 133--155.  Wunderlich H.-J. and Holst S. 2010. Generalized Fault Modeling for Logic Diagnosis. In Wunderlich H.-J.(Ed.) Models in Hardware Testing ISBN: 978-90-481-3281-2 Springer-Verlag Heidelberg 133--155."},{"volume-title":"Proc. 29th IEEE VLSI Test Symp. (VTS), 229--234","author":"Zhang Z.","key":"e_1_3_2_1_34_1","unstructured":"Zhang , Z. , Refauvelet , D. , Greiner , A. , Benabdenbi , M. , and Pecheux , F . 2011. Localization of damaged resources in NoC based shared-memory MP2SOC, using a distributed cooperative configuration infrastructure . In Proc. 29th IEEE VLSI Test Symp. (VTS), 229--234 . Zhang, Z., Refauvelet, D., Greiner, A., Benabdenbi, M., and Pecheux, F. 2011. Localization of damaged resources in NoC based shared-memory MP2SOC, using a distributed cooperative configuration infrastructure. In Proc. 29th IEEE VLSI Test Symp. (VTS), 229--234."},{"key":"e_1_3_2_1_35_1","volume-title":"-J","author":"Zhou J.","year":"2006","unstructured":"Zhou , J. and Wunderlich , H . -J . 2006 . Software-based self-test of processors under power constraints. In Proc. Design, Automation and Test in Europe (DATE) , 430--435. Zhou, J. and Wunderlich, H.-J. 2006. Software-based self-test of processors under power constraints. In Proc. Design, Automation and Test in Europe (DATE), 430--435."}],"event":{"name":"NOCS '15: International Symposium on Networks-on-Chip","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Vancouver BC Canada","acronym":"NOCS '15"},"container-title":["Proceedings of the 9th International Symposium on Networks-on-Chip"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2788708","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2786572.2788708","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:07:38Z","timestamp":1750223258000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2788708"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9,28]]},"references-count":35,"alternative-id":["10.1145\/2786572.2788708","10.1145\/2786572"],"URL":"https:\/\/doi.org\/10.1145\/2786572.2788708","relation":{},"subject":[],"published":{"date-parts":[[2015,9,28]]},"assertion":[{"value":"2015-09-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}