268 questions
Score of 2
0 answers
93 views
RPi3B+ AArch64 kernel in `ttbr1` region: instruction fetch succeeds after `br` to `ttbr1` region, but first data access causes Data Abort (EC=0x25)
I'm writing a kernel in Rust for the Raspberry Pi 3b+ hardware which uses Mini UART for I/O. And so far it had been working wonderfully on QEMU. However, when I finally got access to real hardware to ...
- reputation score 77
Score of 0
0 answers
140 views
AArch64 RPi4b bare-metal OS hangs after MMU enable
I am currently writing a small bare-metal OS for Raspberry Pi 4b for the AArch64/Arm64 architecture.
Unfortunately the OS hangs after enabling the MMU on real hardware. When testing the OS in QEMU ...
- reputation score 1
Score of 2
2 answers
115 views
What happens in an ARM MMU page boundary crossing?
I'm currently making an AArch32 emulator, and I'm trying to make an MMU.
While I got most of the descriptor logic, access permissions, and address translation mechanisms set up, I still have doubts ...
- reputation score 339
Score of 3
1 answer
246 views
is there a way to move a page from a virtual address to another without touching the contents?
I am trying to write some containers in C++ that are supposed to handle big amounts of data.
However I've encountered a bit of a block.
My vector implementation would fall back to being a stable ...
- reputation score 61
Score of 1
1 answer
99 views
why is casting from an unsigned int to a struct that consists of bitfields making up an unsigned int not allowed?
I have looked at the recommendations for both my question and searched for my question's headline but did not find anything related. The line I am confused about is below the comments in mmu.c.
I want ...
user28496108
Score of 4
0 answers
271 views
Find out which translation stage caused an MMU fault exception
(I'm relatively new to aarch64 and to ARM in general, so sorry if this is a dumb question.)
When handling a Data Abort exception (raised in EL1, and taken to EL2 where my hypervisor is running) I need ...
- reputation score 4694
Score of 2
1 answer
374 views
Armv7 MMU on the ZYNQ-7000 not starting the virtualization
Introduction
I have been trying to evaluate the MMU functionality for the Xilinx zynq7000 soc that contains 2 A9-Cortex processors.
Firstly I have tried using the xil_mmu.h library, however after ...
- reputation score 91
Score of 1
1 answer
277 views
Can Arm Trusted Firmware access physical memory directly?
I found the mmio access api in arm-tf/include/lib/mmio.h, it access the addr to perform I/O operations like many other privileged softwares (linux, optee-os, etc.):
static inline void mmio_write_32(...
- reputation score 51
Score of 1
0 answers
212 views
The FAR_EL1 register value is incorrect when an MMU Fault occurs
I am writing an MMU Fault exception handler for my dual-core Cortex-A76 CPU, AArch64 architecture. The OS is ThreadX RTOS, so all code runs at EL1 level.
When an MMU fault is triggered, the ESR_EL1 ...
- reputation score 11
Score of 0
0 answers
981 views
What are the differences between VMID and ASID in the context of virtualization and operating systems?
I'm trying to understand the differences between VMID (Virtual Machine Identifier) and ASID (Address Space Identifier) in the context of virtualization and operating systems.
Refer the (ARM ...
- reputation score 992
Score of 0
1 answer
335 views
If multi-core CPUs share the MMU, can multiple processes run in parallel?
If multi-core CPUs have a dedicated MMU for each core, multiple processes can run in parallel.I want to know what will happen if multi-core CPUs share the MMU.
I guess,if multi-core CPUs share the MMU,...
- reputation score 1
Score of 4
1 answer
639 views
Address translation from supervisor to user mode in RiscV
Assume we are on an hart with M, S and U modes support and we currently are in S mode with virtual address enabled and satp pointing to the current PTE table (the kernel PTE table).
Now assume we want ...
- reputation score 188
Score of 0
0 answers
64 views
Why does it take so long for cpu to write memory after it has obtained the physical address?
https://github.com/torvalds/linux/commit/6ce64428d62026a10cb5d80138ff2f90cc21d367:
cpu0 cpu1 cpu2
---- ---- ----
[ ...
- reputation score 1
Score of 1
0 answers
230 views
What is (special in) the elf format for static-pie? And what preforms the fixups to the GOT?
I'm trying to create some static-pie programs to run in a no-MMU environment.
As far as I can tell static-pie programs are encoded in the ELF format, but use the ET_DYN e_type in their ELF header. ...
- reputation score 323
Score of 1
0 answers
859 views
How are memory addresses translated in QEMU
Im trying to understand how memory works inside a virtual machine, QEMU in particular. I see there are virtual memory, used in a context by CPU and a physical memory, the actual RAM memory. But i dont ...
- reputation score 41
