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ORCIDPeter Dahlgren
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2010 – 2019
- 2012
[c18]Peter Dahlgren:
Social Media and Counter-Democracy: The Contingences of Participation. ePart 2012: 1-12- 2011
- [c17]Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson:
Transition test bring-up and diagnosis on UltraSPARCTM processors. ITC 2011: 1-10
2000 – 2009
- 2009
- [c16]Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu:
Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family. ITC 2009: 1-10 - 2008
- [c15]Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen:
Transition Test on UltraSPARC- T2 Microprocessor. ITC 2008: 1-10 - 2005
- [c14]Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu:
Microprocessor silicon debug based on failure propagation tracing. ITC 2005: 10 - 2003
- [c13]Peter Dahlgren, Paul Dickinson, Ishwar Parulkar:
Latch Divergency In Microprocessor Failure Analysis. ITC 2003: 755-763
1990 – 1999
- 1998
- [c12]Peter Dahlgren:
Switch-level bridging fault simulation in the presence of feedbacks. ITC 1998: 363-371 - 1997
- [c11]Peter Dahlgren:
Switch-level modeling of feedback faults using global oscillation control. VTS 1997: 117-122 - 1996
- [c10]Peter Dahlgren:
Oscillation Control in Logic Simulation using Dynamic Dominance Grahps. DAC 1996: 155-160 - [c9]Peter Dahlgren, Peter Lidén:
A fault model for switch-level simulation of gate-to-drain shorts. VTS 1996: 414-421 - 1995
- [b1]Peter Dahlgren:
Switch-Level Fault Simulation Based on Local Algorithms. Chalmers University of Technology, Gothenburg, Sweden, 1995 - [c8]Peter Dahlgren, Peter Lidén:
A Switch-level Algorithm for Simulation of Transients in Combinational Logic. FTCS 1995: 207-216 - [c7]Peter Dahlgren:
A multiple-dominance switch-level model for simulation of short faults. ICCAD 1995: 674-680 - [c6]Peter Lidén, Peter Dahlgren:
Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. ISCAS 1995: 2124-2127 - [c5]Peter Lidén, Peter Dahlgren:
Switch-level modeling of transistor-level stuck-at faults. VTS 1995: 208-215 - 1994
- [j1]Johan Karlsson, Peter Lidén, Peter Dahlgren, Rolf Johansson, Ulf Gunneflo:
Using heavy-ion radiation to validate fault-handling mechanisms. IEEE Micro 14(1): 8-23 (1994) - [c4]Peter Dahlgren, Peter Lidén:
Modeling of Intermediate Node States in switch-Level Networks. DAC 1994: 722-727 - [c3]Peter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson:
On Latching Probability of Particle Induced Transients in Combinational Networks. FTCS 1994: 340-349 - 1993
- [c2]Peter Dahlgren, Peter Lidén:
Efficient modeling of switch-level networks containing undetermined logic node states. ICCAD 1993: 746-752 - 1992
- [c1]Peter Lidén, Peter Dahlgren, Jan Torin:
Transistor Fault Coverage for Self-Testing CMOS Checkers. ITC 1992: 476-485
Coauthor Index
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