default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCODES+ISSS 2015: Amsterdam, Netherlands
- Gabriela Nicolescu, Andreas Gerstlauer:
2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015. IEEE 2015, ISBN 978-1-4673-8321-9 - Florian Kriebel, Arun Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, Muhammad Shafique
, Jörg Henkel:
R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores. 1-10 - Chun-Ta Lin, Yuan-Hao Chang, Tei-Wei Kuo, Hung-Sheng Chang, Hsiang-Pang Li:
How to improve the space utilization of dedup-based PCM storage devices? 11-20 - Mungyu Son, Junwhan Ahn, Sungjoo Yoo:
A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones. 21-29 - Mohammad Abdullah Al Faruque, Francesco Regazzoni, Miroslav Pajic:
Design methodologies for securing cyber-physical systems. 30-36 - Sudeep Pasricha, Viney Ugave, Charles W. Anderson, Qi Han:
LearnLoc: A framework for smart indoor localization with embedded mobile devices. 37-44 - Pirmin Vogel, Andrea Marongiu, Luca Benini:
Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. 45-54 - Bowen Zheng, Yue Gao, Qi Zhu, Sandeep K. Gupta:
Analysis and optimization of soft error tolerance strategies for real-time systems. 55-64 - Jelena Spasic, Di Liu, Emanuele Cannella, Todor P. Stefanov:
Improved hard real-time scheduling of CSDF-modeled streaming applications. 65-74 - Mohammad Salehi, Muhammad Shafique, Florian Kriebel, Semeen Rehman, Mohammad Khavari Tavana, Alireza Ejlali, Jörg Henkel:
dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations. 75-82 - Kuangya Zhai, Richard Townsend, Lianne Lairmore, Martha A. Kim, Stephen A. Edwards:
Hardware synthesis from a recursive functional language. 83-93 - Marco D. Santambrogio, José L. Ayala, Simone Campanoni, Riccardo Cattaneo, Gianluca C. Durelli, Matteo Ferroni, Alessandro Antonio Nacci, Josué Pagán, Marina Zapater, Mónica Vallejo:
Power-awareness and smart-resource management in embedded computing systems. 94-103 - Santiago Pagani, Muhammad Shafique, Heba Khdr, Jian-Jia Chen, Jörg Henkel:
seBoost: Selective boosting for heterogeneous manycores. 104-113 - Srinath Arunachalam, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu:
An online wear state monitoring methodology for off-the-shelf embedded processors. 114-123 - Eunhyeok Park, Dongyoung Kim, Soobeom Kim, Yong-Deok Kim, Gunhee Kim, Sungroh Yoon, Sungjoo Yoo:
Big/little deep neural network for ultra low power inference. 124-132 - Farzad Samie, Lars Bauer, Jörg Henkel:
An approximate compressor for wearable biomedical healthcare monitoring systems. 133-142 - Caio Hoffman, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo:
Computer security by hardware-intrinsic authentication. 143-152 - Namita Sharma, Preeti Ranjan Panda, Francky Catthoor:
Energy efficient FFT implementation through stage skipping and merging. 153-162 - Vítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini:
Fast parallel application and multiprocessor design space exploration from sequential code. 163-172 - Tiago Mück, Santanu Sarma, Nikil D. Dutt:
Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency. 173-182 - Ashraf El Antably, Olivier Gruber, Frédéric Rousseau, Nicolas Fournel:
Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures. 183-192 - Alessandro Danese, Luca Piccolboni, Graziano Pravadelli:
A parallelizable approach for mining likely invariants. 193-201 - Sunha Ahn, Sharad Malik, Aarti Gupta:
Completeness bounds and sequentialization for model checking of interacting firmware and hardware. 202-211 - Mojtaba Ebrahimi, Nour Sayed, Maryam Rashvand, Mehdi Baradaran Tahoori:
Fault injection acceleration by architectural importance sampling. 212-219 - Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin:
The shift to multicores in real-time and safety-critical systems. 220-229
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-08-12 22:56 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated, funded, and maintained by:
Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.
