{"id":"https://openalex.org/W2101456474","doi":"https://doi.org/10.1109/92.894162","title":"Interfacing synchronous and asynchronous modules within a high-speed pipeline","display_name":"Interfacing synchronous and asynchronous modules within a high-speed pipeline","publication_year":2000,"publication_date":"2000-10-01","ids":{"openalex":"https://openalex.org/W2101456474","doi":"https://doi.org/10.1109/92.894162","mag":"2101456474"},"language":"en","primary_location":{"id":"doi:10.1109/92.894162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/92.894162","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036319882","display_name":"A.E. Sjogren","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.E. Sjogren","raw_affiliation_strings":["Smurfit-Stone Container Corporation, USA","Smurfit-Stone Container Corp., Salt Lake City, UT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Smurfit-Stone Container Corporation, USA","institution_ids":[]},{"raw_affiliation_string":"Smurfit-Stone Container Corp., Salt Lake City, UT, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":null,"display_name":"C.J. Myers","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.J. Myers","raw_affiliation_strings":["Department of Electrical Engineering, University of Utah, USA","University of Utah, Salt Lake City"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Utah, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"University of Utah, Salt Lake City","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.7434,"has_fulltext":false,"cited_by_count":55,"citation_normalized_percentile":{"value":0.90176735,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"8","issue":"5","first_page":"573","last_page":"583"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7622381448745728},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.6908223032951355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6575413942337036},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6345828771591187},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.6294094324111938},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5809179544448853},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5771092772483826},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.504004180431366},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.484413206577301},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.4431871175765991},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4409826397895813},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.42910903692245483},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41564658284187317},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41146695613861084},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3941877484321594},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3913334906101227},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3883081078529358},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3737233877182007},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3260650038719177},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2588280439376831},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19628673791885376},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.17721310257911682},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.14437386393547058}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7622381448745728},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.6908223032951355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6575413942337036},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6345828771591187},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.6294094324111938},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5809179544448853},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5771092772483826},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.504004180431366},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.484413206577301},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.4431871175765991},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4409826397895813},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42910903692245483},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41564658284187317},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41146695613861084},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3941877484321594},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3913334906101227},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3883081078529358},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3737233877182007},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3260650038719177},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2588280439376831},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19628673791885376},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.17721310257911682},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.14437386393547058},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/92.894162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/92.894162","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.35.1880","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.35.1880","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.async.elen.utah.edu/publications/TVLSI2.ps.gz","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.48.8142","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.8142","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.async.elen.utah.edu/publications/ARVLSI97.ps.gz","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8199999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309398","display_name":"California Institute of Technology","ror":"https://ror.org/05dxps055"},{"id":"https://openalex.org/F4320310050","display_name":"University of Utah","ror":"https://ror.org/03r0ha626"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1609287256","https://openalex.org/W1722620788","https://openalex.org/W1943426535","https://openalex.org/W2033045135","https://openalex.org/W2052006175","https://openalex.org/W2131894786","https://openalex.org/W2164944039","https://openalex.org/W2167775755","https://openalex.org/W2293768995","https://openalex.org/W2911717499","https://openalex.org/W6977921150"],"related_works":["https://openalex.org/W2050222423","https://openalex.org/W60393894","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W2095703739","https://openalex.org/W794031490","https://openalex.org/W2378481815","https://openalex.org/W2349909378","https://openalex.org/W2793650255","https://openalex.org/W158833317"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,11,23,27,85,144],"new":[4],"technique":[5],"for":[6],"integrating":[7],"asynchronous":[8,82],"modules":[9,83],"within":[10],"high-speed":[12,86],"synchronous":[13,79,100],"pipeline.":[14],"Our":[15,71],"design":[16,48,152],"eliminates":[17],"potential":[18],"metastability":[19],"problems":[20],"by":[21,26,90,123,132],"using":[22,155],"clock":[24,38,64],"generated":[25],"stoppable":[28],"ring":[29,59,107],"oscillator,":[30],"which":[31],"is":[32,153],"capable":[33],"of":[34,77,98,105],"driving":[35],"the":[36,46,58,63,78,96,99,103,106,115,120,124,133,156],"large":[37],"load":[39],"found":[40],"in":[41,84,147,162],"present":[42],"day":[43],"microprocessors.":[44],"Using":[45],"ATACS":[47],"tool,":[49],"we":[50],"designed":[51],"highly":[52],"optimized":[53],"transistor-level":[54],"circuits":[55],"to":[56,143],"control":[57],"oscillator":[60,108],"and":[61,65,113],"generate":[62],"handshake":[66],"signals":[67],"with":[68],"minimal":[69],"overhead.":[70],"interface":[72,151],"architecture":[73],"requires":[74],"no":[75],"redesign":[76],"circuitry.":[80],"Incorporating":[81],"pipeline":[87],"improves":[88],"performance":[89],"exploiting":[91],"data-dependent":[92],"delay":[93],"variations.":[94],"Since":[95],"speed":[97,104,121],"circuitry":[101],"tracks":[102],"under":[109],"different":[110],"processes,":[111],"temperatures,":[112],"voltages,":[114],"entire":[116],"chip":[117],"operates":[118],"at":[119],"dictated":[122],"current":[125],"operating":[126],"conditions,":[127],"rather":[128],"than":[129],"being":[130],"governed":[131],"worst":[134],"case":[135],"conditions.":[136],"These":[137],"two":[138],"factors":[139],"together":[140],"can":[141],"lead":[142],"significant":[145],"improvement":[146],"average-case":[148],"performance.":[149],"The":[150],"simulated":[154],"0.6-/spl":[157],"mu/m":[158],"HP":[159],"CMOS14B":[160],"process":[161],"HSPICE.":[163]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
